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OKI Semiconductor ML9204-xx
GENERAL DESCRIPTION
PEDL9204-02
Issue Date: Oct. 12, 2004
Preliminary
5 x 7 Dot Character x 24-Digit x 2-Line Display Controller/Driver with Character RAM (Built-in Key Scan)
The ML9204-xx is a 5 x 7 dot matrix type vacuum fluorescent display tube controller driver IC which displays characters, numerics and symbols of a maximum of 24 digits x 2 lines. Dot matrix vacuum fluorescent display tube drive signals are generated by serial data sent from a micro-controller. A display system is easily realized by internal ROM and RAM for character display. Built-in key scan for 3-channel encoder type rotary switch and 5 x 6 matrix key switch allow the user to receive each switch input. The ML9204-xx has low power consumption since it is made by CMOS process technology. -01 is available as a general-purpose code. Custom codes are provided on customer's request.
FEATURES
: 3.3 V10% or 5.0 V10% * Logic power supply (VDD) * VFD tube drive power supply (VSEG, VCOM ) : 20 to 60 V * VFD driver output current (VFD driver output can be connected directly to the VFD tube. No pull-down resistor is required.) * Segment driver (SEGA1 to A35, SEGB1 to B35) Only one driver output is high : -5 mA (VSEG = 60 V) All the driver outputs are high : -350 mA (VSEG = 60 V) * Segment driver (ADA, ADB) : -15 mA (VSEG = 60 V) * Grid driver (COM1 to 24) : -25 mA (VCOM = 60 V) * Content of display SEGA1 to SEGA35 and ADA * CGROM_A : 5 x 7 dots 240 types (character data) * CGRAM_A : 5 x 7 dots 16 types (character data) * ADRAM_A : 24 (display digit)x 1 bit (symbol data; can be used for a cursor.) * DCRAM_A : 24 (display digit) x 8 bits (register for character data display) SEGB1 to SEGB35 and ADB * CGROM_B : 5 x 7 dots 240 types (character data) * CGRAM_B : 5 x 7 dots 16 types (character data) * ADRAM_B : 24 (display digit)x 1 bit (symbol data; can be used for a cursor.) * DCRAM_B : 24 (display digit) x 8 bits (register for character data display) * Display control function * GCRAM : Simultaneous output of COM1 to 24 can be set in 1 grid. * Display digits : 1 to 24 digits (9- to 24-bit arbitrary setting) * Display duty (brightness adjustment) : 0/1024 to 960/1024 stages * All lights ON/OFF * 5 interfaces with microcontroller:DI/O, CS, CP, RESET, INT * Built-in key scan circuit for 5 x 6 matrix key switch * Built-in key scan circuit for 3-channel encoder type rotary switch * Built-in oscillation circuit Crystal oscillation or ceramic oscillation: 4.0 MHz (Typ) * Standby function Inhibiting the oscillator circuit provides low power consumption. * Package options: 128-pin plastic QFP (QFP128-P-1420-0.50-K) (ML9204-xxGA)
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BLOCK DIAGRAM
VSEG VCOM VDD D-GND L-GND RESET CS CP
DCRAM_A 24w x 8b
CGROM_A 240w x 35b Segment Driver CGRAM_A 16w x 35b
SEGA1
SEGA35 Segment Driver
8bit Shift Register DCRAM_B 24w x 8b
ADRAM_B 24w x 1b
ADA
CGROM_B 240w x 35b Segment Driver CGRAM_B 16w x 35b
SEGB1
SEGB35 Segment Driver
Command Decoder Control Circuit Address Selector Write Address Counter
Timing Generator 2
ADRAM_B 24w x 1b
ADB
GCRAM 24w x 24b Grid Driver
COM1
DI/O
Read Address Counter Digit Control Duty Control
COM24
Timing Generator 1
OSC0 Oscillator OSC1 5 x 6 Key Scan and Encoder Switch Interface INT
ROW1
ROW5 COL1
COL6 A1 B1 A2 B2 A3 B3
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PIN CONFIGURATION (TOP VIEW)
126 SEGB9 125 SEGB10 124 SEGB11 123 SEGB12 110 SEGB25 109 SEGB26 108 SEGB27 107 SEGB28 122 SEGB13 121 SEGB14 120 SEGB15 119 SEGB16 118 SEGB17 106 SEGB29 105 SEGB30 115 SEGB20 114 SEGB21 113 SEGB22 117 SEGB18 116 SEGB19 128 SEGB7 127 SEGB8 112 SEGB23 111 SEGB24 104 SEGB31 103 SEGB32 102 SEGB33 101 SEGB34 100 SEGB35 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 59 60 SEGA10 42 SEGA11 43 SEGA12 44 SEGA13 45 SEGA21 53 SEGA22 54 SEGA23 55 SEGA24 56 SEGA25 57 SEGA29 61 SEGA30 62 SEGA31 63 41 SEGA15 47 SEGA16 48 39 40 58 SEGA14 46 SEGA17 49 SEGA18 50 SEGA19 51 SEGA20 52 SEGA32 64 ADB VSEG D-GND VDD INT DI/O CP CS RESET B3 A3 B2 A2 B1 A1 COL6 COL5 COL4 COL3 COL2 COL1 ROW5 ROW4 ROW3 ROW2 ROW1 OSC1 OSC0 L-GND D-GND VSEG ADA SEGA35 SEGA34 SEGA33
SEGB6 SEGB5 SEGB4 SEGB3 SEGB2 SEGB1 VCOM COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
COM10 17 COM11 18 COM12 19 COM13 20 COM14 21 COM15 22 COM16 23 COM17 24 COM18 COM19 25 26
COM20 27 COM21 28 COM22 COM23 29 30
COM24 31 VCOM 32 SEGA1 33 SEGA2 34 SEGA3 35 SEGA4 36 SEGA5 37 SEGA6 38
SEGA27
SEGA7 SEGA8
SEGA9
128-Pin Plastic QFP
SEGA26
SEGA28
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PIN DESCRIPTION
Pin 33 to 67 1 to 6 100 to 128 8 to 31 Symbol SEGA1 to A35 SEGB1 to B35 O VFD tube anode electrode Type Connects to Description VFD tube anode electrode drive output. Directly connected to fluorescent display tube and a pull-down resistor is not necessary. IOH < -5 mA VFD tube grid electrode drive output. Directly connected to fluorescent display tube and a pull-down resistor is not necessary. IOH < -25 mA VFD tube anode electrode drive output. Directly connected to fluorescent display tube and a pull-down resistor is not necessary. IOH < -15 mA VDD-L-GND are power supplies for internal logic. VCOM-D-GND are power supplies for driving VFD tube grid. VCOM-D-GND are power supplies for driving VFD tube anode. Use the same power supply for L-GND and D-GND. Serial data input-output (positive logic). Data is input and output to sift register synchronized with the rise of shift clock. When Inputting data input from the LSB. Shift clock input. Serial data is shifted on the rising edge of CP. Chip select input. Serial data transfer is disabled when CS pin is "H" level. Output pin for interrupt signal to micro controller. When depression or release of key matrix switch is detected, key scanning starts and when 1 cycle is completed, this pin becomes high level. Upon receiving encoder type rotary switch input, this pin becomes high level. The INT pin remains at high level until the key scan stop mode is selected.. Encoder type rotary switch input pins. All inputs possess chattering absorption function of 256us period. Those inputs must be tied to ground when they are not used. Input pins for return signal from key matrix with built-in pull-up resister. When input is low level, the key matrix switch is regarded as being pressed. Dose not have chattering absorption function.
COM1 to 24
O
VFD tube grid electrode
68 99 96 71 7,32 69,98 70,97
ADA O ADB VDD L-GND VCOM VSEG D-GND --
VFD tube anode electrode
Power supply
94
DI/O
I/O
Micro controller
93 92
CP CS
l l
Micro controller Micro controller
95
INT
O
Micro controller
85,86 87,88 89,90
A1,B1 A2,B2 A3,B3
l
Rotary switch
79 to 84
COL1 to 6
I
Key matrix
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74 to 78
ROW1 to 5
O
Key matrix
Key matrix scan signal output pins. Normally low level is output. Key scanning starts by detecting depression or release of key matrix switch and continues until selection of key scan stop mode. When key scan stop mode is selected, all outputs of ROW1 to 5 return to low level. Reset input. "Low" initializes all the functions. Initial status is as follows. * Address of each RAM .............. address "00"H * Data of each RAM ................... Content is undefined * Display digit............................. 24 digits * Brightness adjustment ............. 0/1024 * All lights ON or OFF ................ OFF mode * ROW1 to 5 .............................. becomes low level * INT.......................................... becomes low level Pins for self-oscillation. (Do not apply external clocks to these pins.) Connect these pins to the crystal and capacitors or to the ceramic resonator and capacitors. The target oscillation frequency is 4.0MHz. (The device has an internal feedback resister.) VDD 3.3V 5.0V Typical 1Mohm 0.4Mohm
91
RESET
l
Micro controller
72
OSC0
l Crystal or ceramic resonator
73
OSC1
O
* For information regarding the oscillator contact the manufacturer of the oscillator. * As regards the circuit, refer to the Application Circuit.
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ABSOLUTE MAXIMUM RATINGS
Parameter Supply Voltage (1) Supply Voltage (2) Input Voltage Power Dissipation Storage Temperature Symbol VDD VSEG VCOM VIN PD TSTG lO1 lO2 Output Current lO3 IO4 Condition -- -- -- -- Ta 85C -- COM1 to COM24 ADA, ADB SEGA1 to SEGA35, SEGB1 to SEGB35 ROW1 to 5 / INT Rating -0.3 to +6.5 -0.3 to +70 -0.3 to +70 -0.3 to VDD+0.3 470 *1) -55 to +150 -50 to +2.0 -30 to +2.0 -10 to +2.0 -2.0 to +2.0 Unit V V V V mW C mA mA mA mA
*1) When use two or more COM, be careful of the following things. The junction temperature which can be found by the following formula does not exceed 120. Tj = (Px 85C /W)+Ta (P is the maximum power consumption of IC.)
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Condition When the power supply voltage is 5.0 V (typ.) When the power supply voltage is 3.3 V (typ.) -- -- Oscillation DIGIT = 1 to 24, oscillation -- Min. 4.5 3.0 20 20 3.5 142 -40 Typ. 5.0 3.3 -- -- 4.0 163 -- Max. 5.5 3.6 60 60 4.5 183 +85 Unit V V V V MHz Hz C
Supply Voltage (1)
VDD
Supply Voltage (2) Operating Frequency Frame Frequency Operating Temperature
VSEG VCOM fOSC fFR TOP
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ELECTRICAL CHARACTERISTICS
DC Characteristics (VDD = 5.0 V10%)
(VDD = 5.0 V10%, VSEG and VCOM = 20 to 60 V, Ta = -40 to +85C, unless otherwise specified) Parameter High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Symbol VIH VIL IIH IIL1 IIL2 VOH1 VOH2 High Level Output Voltage VOH3 VOH4 Low Level Output Voltage VOL1 VOL2 IDD1 Supply Current (1) IDISP1 IDISP2 Supply Current (2) IDDS IDISPS VSEG, VCOM VDD VSEG, VCOM Applied pin *1 *1 *1 *2 COL1 to 6 COM1 to 24 ADA, ADB SEGA1 to A35 SEGB1 to B35 INT, ROW1 to 5 *3 Condition VDD = 5.0 V10% VDD = 5.0 V10% VIH = VDD VIL = 0.0 V VDD = 5.0 V10%, VIL = 0.0 V VCOM = 60 V, IOH1 = -25 mA VSEG = 60 V, IOH2 = -15 mA VSEG = 60 V, IOH3 = -5 mA VDD = 5.0 V10%, IOH4 = -450 A -- VDD = 5.0 V10%, fOSC = 4.0 MHz fOSC = 4.0 All output lights ON MHz, All output lights OFF no load In standby mode Min. 0.7 VDD -- -1.0 -1.0 -450 VCOM - 2.0 VSEG - 2.0 VSEG - 2.0 VDD - 0.2 -- -- -- -- -- -- -- Max. -- 0.3 VDD +1.0 +1.0 -100 -- -- -- -- 1.0 0.2 6.0 1.0 200 1.0 20.0 Unit V V A A A V V V V V V mA mA A A A
INT, ROW1 to 5 VDD =5.0 V10%, IOL2 = 450 A VDD
*1) CS, CP, DI/O, RESET, COL1 to 6 *2) CS, CP, DI/O, RESET *3) SEGA1 to A35, SEGB1 to B35, ADA, ADB, COM1 to 24
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DC Characteristics (VDD = 3.3 V10%)
(VDD = 3.3 V10%, VSEG and VCOM = 20 to 60 V, Ta = -40 to +85C, unless otherwise specified) Parameter High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Symbol VIH VIL IIH IIL1 IIL3 VOH1 VOH2 High Level Output Voltage VOH3 VOH5 Low Level Output Voltage VOL1 VOL2 IDD2 Supply Current (1) IDISP1 IDISP2 Supply Current (2) IDDS IDISPS VSEG, VCOM VDD VSEG, VCOM Applied pin *1 *1 *1 *2 COL1 to 6 COM1 to 24 ADA, ADB SEGA1 to A35 SEGB1 to B35 INT, ROW1 to 5 *3 Condition VDD = 3.3 V10% VDD = 3.3 V10% VIH = VDD VIL = 0.0 V VDD = 3.3 V10%, VIL = 0.0 V VCOM = 60 V, IOH1 = -25 mA VSEG = 60 V, IOH2 = -15 mA VSEG = 60 V, IOH3 = -5 mA VDD = 3.3 V10%, IOH5 = -120 A -- VDD = 3.3 V10%, fOSC = 4.0 MHz fOSC = 4.0 All output lights ON MHz, All output lights OFF no load In standby mode Min. 0.8 VDD -- -1.0 -1.0 -120 VCOM - 2.0 VSEG - 2.0 VSEG - 2.0 VDD - 0.2 -- -- -- -- -- -- -- Max. -- 0.2 VDD +1.0 +1.0 -25 -- -- -- -- 1.0 0.2 4.0 1.0 200 1.0 20.0 Unit V V A A A V V V V V V mA mA A A A
INT, ROW1 to 5 VDD = 3.3 V10%, IOL3 = 120 A VDD
*1) CS, CP, DI/O, RESET, COL1 to 6 *2) CS, CP, DI/O, RESET *3) SEGA1 to A35, SEGB1 to B35, ADA, ADB, COM1 to 24
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AC Characteristics
(VDD = 5.0 V10%, or VDD = 3.3 V10%,VSEG and VCOM = 20 to 60 V, Ta = -40 to +85C unless otherwise specified) Parameter CP Frequency CP Pulse Width D/A Setup Time D/A Hold Time CS Setup Time CS Hold Time CS Wait Time Data Processing Time RESET Pulse Width RESET Time D/A Wait Time All Output Slew Rate OSC Duty Ratio Oscillation Rise Time Symbol fC tCW tDS tDH tCSS tCSH tCSW tDOFF tWRES tRSON tRSOFF tR tF duOSC tOSCON Cl = 100 pF -- -- Condition -- -- -- -- -- Oscillating state -- Oscillating state When RESET signal is input from microcontroller etc. externally -- -- tR = 20 to 80% tF = 80 to 20% Min. -- 200 200 200 200 8 200 4 200 tOSCON 200 -- -- 40 Max. 2.0 -- -- -- -- -- -- -- -- -- -- 2.0 2.0 60 *1 ns s s % Unit MHz ns ns ns ns s ns s ns
*1 tOSCON (oscillation rise time) differs with the oscillator pin used. As regards oscillation rise time, refer to the data of oscillator used.
Key Scan Characteristics
(VDD = 5.0V10%, or VDD = 3.3V10%, VSEG and VCOM = 20 to 60 V, Ta = -40 to +85C unless otherwise specified) Parameter Key Scan Time Key Scan Pulse Width Symbol tSCAN tWSCAN Condition fOSC = 3.5 to 4.5 MHz Min. 142.2 28.4 Typ. 160 32 Max. 182.8 36.6 Unit s s
Rotary Switch Characteristics
(VDD = 5.0V10%, or VDD = 3.3V10%, VSEG and VCOM = 20 to 60 V, Ta = -40 to +85C unless otherwise specified) Parameter Phase Input Time Phase Input Fixed Time Symbol tABW tABH Condition fOSC = 3.5 to 4.5 MHz Min. 1.2 Typ. -- Max. -- Unit ms
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TIMING DIAGRAMS
Symbol VIH VIL VDD = 5.0 V 10% 0.7 VDD 0.3 VDD VDD = 3.0 V 10% 0.8 VDD 0.2 VDD
Data Input Timing
tCSS CS 1/fC tCW tCW tCSH VIH VIL VIH VIL tCSW VIH VIL
CP tDS DI/O
(INPUT)
tDOFF tDH
VALID VALID
VALID VALID
Data Output Timing
CS CP tCSS tCSH TPD TPD TPD TPD -VIH -VIL -VIH -VIL
DI/O
(OUTPUT)
VALID
VALID
VALID
VALID
VALID
-VIH -VIL
Output Timing
All Output Driver 5) tR tF -0.8 (VSEG, VCOM) -0.2 (VSEG, VCOM)
OSC Timing
duOSC=Bx100/(A+B)
OSC1 A B
-0.5VDD
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Standby Mode Release Timing
-VIH CS CP
200nsec or more
-VIL -VIH tRSON -VIL -VIH VALID -VIL
DI/O
OSC0 tOSCON
0.9Vp-p
Vp-p (stationary state oscillation level)
Reset Timing * After a VDD injection should surely input a reset signal.
VDD tRSON RESET tRSOFF DI/O VALID -VIL tWRES -0.8 VDD -0.0 V -VIH -VIL -VIH
Key Scan Timing
tSCAN ROW1 tWSCAN ROW2
ROW3
ROW4
ROW5
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Rotary Switch Input Timing
A
B tABW tABH tABH tABW tABW
Digit Output Timing (24-Digit,960/1024-Duty)
*:T = 1/fOSC Frame cycle t1 = 24576T (fOSC = 4.0 MHz : t1 = 6.144ms) Display t2 = 960T (fOSC = 4.0 MHz : t2 = 240s) (fOSC = 4.0 MHz : t3 = 16s) Blank Timing t3 = 64T VCOM D-GND
COM1 COM2 COM3 COM4 COM5
COM20 COM21 COM22 COM23 COM24 ADA, ADB, SEGA1~A35, SEGB1~B35 VSEG D-GND
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FUNCTIONAL DESCRIPTION
Commands List
Command 1 DCRAM_A data write LSB 1st byte LSB 2nd byte MSB MSB B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 * * * * 1 0 0 0 C0 C1 C2 C3 C4 C5 C6 C7 C0 C5 C10 C15 C20 C25 C30 C1 C6 C11 C16 C21 C26 C31 2 CGRAM_A data write 0 0 0 0 0 1 0 0 C2 C7 C12 C17 C22 C27 C32 C3 C8 C13 C18 C23 C28 C33 C4 C9 C14 C19 C24 C29 C34 3 4 ADRAM_A data write GCRAM data write * * * * * * * * 1 0 1 0 0 1 0 0 C0 * * * * * * * * * * * * 2nd byte 3rd byte 4th byte 5th byte 6th byte
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 5 6 7 9 Display duty set Number of digits set All lights ON/OFF DCRAM_B data write D0 D1 * * 1 0 1 1 0 1 1 0 1 1 1 0 0 0 0 1 C0 C1 C2 C3 C4 C5 C6 C7 C0 C5 C10 C15 C20 C25 C30 C1 C6 C11 C16 C21 C26 C31 A CGRAM_B data write 0 0 0 0 0 1 0 1 C2 C7 C12 C17 C22 C27 C32 C3 C8 C13 C18 C23 C28 C33 C4 C9 C14 C19 C24 C29 C34 B C D F 0 ADRAM_B data write Key scan stop Key data output Standby mode Test Mode(Note) * * * * * * * * * * * * * * * * 1 0 1 1 0 1 0 0 1 0 0 1 1 1 0 1 1 1 1 0 *
Xn Cn Dn Kn H L : Don't care : Address specification for each RAM : Character code specification for each RAM : Display duty specification : Number of digits specification : All lights ON instruction : All lights OFF instruction
D2 D3 D4 D5 D6 D7 D8 D9
K0 K1 K2 K3 L * H * * * * *
* * * * * *
2nd byte 3rd byte 4th byte 5th byte 6th byte
C0
*
*
*
*
*
*
Refer to item D of command and function description.
When data is written to RAM (DCRAM, CGRAM, ADRAM, and GCRAM) continuously, addresses are internally incremented automatically. Therefore it is not necessary to specify the 1st byte to write RAM data for the 2nd and later bytes. Note: The test mode is used for inspection before shipment. It is not a user function. The user cannot use this command. Enter commands 1 to 7, 9 to D, and F alone in the way described on the next page and the following pages. (The operation of this device cannot be guaranteed if other commands are used.
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Positional Relationship Between SEGn and ADn (one digit)
C0
C0
SEGA1
ADA
Corresponds to the 2nd byte of the ADRAM_A data write command. C4
SEGA5
C1
SEGA2
C2
SEGA3
C3
SEGA4
C5
SEGA6
C6
SEGA7
C7
SEGA8
C8
SEGA9
C9
SEGA10
C10
SEGA11
C11
SEGA12
C12
SEGA13
C13
SEGA14
C14
SEGA15
C15
SEGA16
C16
SEGA17
C17
SEGA18
C18
SEGA19
C19
SEGA20
C20
SEGA21
C21
SEGA22
C22
SEGA23
C23
SEGA24
C24
SEGA25
C25
SEGA26
C26
SEGA27
C27
SEGA28
C28
SEGA29
C29
SEGA30
C30
SEGA31
C31
SEGA32
C32
SEGA33
C33
SEGA34
C34
SEGA35
Corresponds to the 6th byte of the CGRAM_A data write command. Corresponds to the 5th byte of the CGRAM_A data write command. Corresponds to the 4th byte of the CGRAM_A data write command. Corresponds to the 3rd byte of the CGRAM_A data write command. Corresponds to the 2nd byte of the CGRAM_A data write command.
C0
C0
SEGB1
ADB
Corresponds to the 2nd byte of the ADRAM_B data write command. C4
SEGB5
C1
SEGB2
C2
SEGB3
C3
SEGB4
C5
SEGB6
C6
SEGB7
C7
SEGB8
C8
SEGB9
C9
SEGB10
C10
SEGB11
C11
SEGB12
C12
SEGB13
C13
SEGB14
C14
SEGB15
C15
SEGB16
C16
SEGB17
C17
SEGB18
C18
SEGB19
C19
SEGB20
C20
SEGB21
C21
SEGB22
C22
SEGB23
C23
SEGB24
C24
SEGB25
C25
SEGB26
C26
SEGB27
C27
SEGB28
C28
SEGB29
C29
SEGB30
C30
SEGB31
C31
SEGB32
C32
SEGB33
C33
SEGB34
C34
SEGB35
Corresponds to the 6th byte of the CGRAM_B data write command. Corresponds to the 5th byte of the CGRAM_B data write command. Corresponds to the 4th byte of the CGRAM_B data write command. Corresponds to the 3rd byte of the CGRAM_B data write command. Corresponds to the 2nd byte of the CGRAM_B data write command.
COMn
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Data Transfer Method and Command Write Method Display control command and data are written by an 8-bit serial transfer. Write timing is shown in the figure below. Setting the CS pin to "Low" level enables a data transfer. Data is 8 bits and is sequentially input into the DI/O pin from LSB (LSB first). As shown in the figure below, data is read by the shift register at the rising edge of the shift clock, which is input into the CP pin. If 8-bit data is input, internal load signals are automatically generated and data is written to each register and RAM. Therefore it is not necessary to input load signals from the outside. Setting the CS pin to "High" disables data transfer. Data input from the point when the CS pin changes from "High" to "Low" is recognized in 8-bit units.
CS CP
tDOFF
tCSH
B0 B1B2 B3 B4 B5 B6 B7 DA LSB 1st byte MSB
B0 B1B2 B3 B4 B5 B6 B7 LSB 2nd byte MSB
B0 B1B2 B3 B4 B5 B6 B7 LSB 3rd byte MSB
When data is written to DCRAM*
Command and address data
Character code data
Character code data of the next address
* When data is written to RAM (DCRAM, ADRAM, CGRAM, GCRAM) continuously, addresses are internally incremented automatically. Therefore it is not necessary to specify the 1st byte to write RAM data for the 2nd and later bytes.
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Data Outputting and Command Writing In an operation to read key scan data, when CS goes "Low" after Key Data Output Mode is entered, the DI/O pin changes modes to OUTPUT and key data is output in synchronization with the rise of Shift Lock. The waveforms to read key data are shown blow. The DI/O pin enters the INPUT mode when the CS pin is set to "High" after key data is output.
CS CP
tCSH
DI/O
B0 B1 B2 B3 B4 B5 B6 B7 LSB MSB
B0 B1 B2 B3 B4 B5 B6 B7 LSB MSB VALID
Keyscan stop
Key data output mode
Data output (42-bit)
Reset Function Reset is executed when the RESET pin is set to "L", (when turning power on, for example) and initializes all functions. Initial status is as follows. * * * * * * * * * Address of each RAM ..................... address "00"H Data of each RAM .......................... All contents are undefined Display digit ................................... 24 digits Brightness adjustment..................... 0/1024 All display lights ON or OFF .......... OFF mode Segment output ............................... All segment outputs go "Low" AD output....................................... All AD outputs go "Low" ROW1 to 5...................................... All ROW outputs go "Low" INT................................................. INT goes "Low."
Be sure to execute the reset operation when turning power on and set again according to "Setting Flowchart" after reset.
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Description of Commands and Functions 1,9. DCRAM data write (Writes the character code of CGROM and CGRAM.) DCRAM (Data Control RAM) has a 5-bit address to store character code of CGROM and CGRAM. The character code specified by DCRAM is converted to a 5 x 7 dot matrix character pattern via CGROM or CGRAM. (The DCRAM can store 24 characters.) [Command format]
LSB MSB
B0 B1 B2 B3 B4 B5 B6 B7 1st byte (1st) *
LSB
0: Select DCRAM_A 1: Select DCRAM_B : Selects DCRAM data write mode
*
*
*
1
0
0 0/1
MSB
B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (2nd) C0 C1 C2 C3 C4 C5 C6 C7 : Specifies character code of CGROM and CGRAM (Written into DCRAM address 00H)
To specify the character code of CGROM and CGRAM continuously to the next address, specify only character code as follows. The addresses of DCRAM are automatically incremented. Specification of an address is unnecessary.
LSB MSB
B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (3rd) C0 C1 C2 C3 C4 C5 C6 C7
LSB MSB
: Specifies character code of CGROM and CGRAM (Written into DCRAM address 01H)
B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (4th) C0 C1 C2 C3 C4 C5 C6 C7 : Specifies character code of CGROM and CGRAM (Written into DCRAM address 02H)
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (25th) C0 C1 C2 C3 C4 C5 C6 C7 : Specifies character code of CGROM and CGRAM (Written into DCRAM address 17H)
A character code setup of CGROM to 24-Digit and CGRAM is completion in the above work. Furthermore, you have to specify the character codes of a dummy to be DCRAM and 18H-1FH to perform a character code setup from DCRAM address 00H continuously. (In order to carry out the increment of the address of DCRAM automatically and to set a DCRAM address to 00H.)
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LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (26th) C0 C1 C2 C3 C4 C5 C6 C7
8 times enforcement
: CGROM of a dummy and the character code of CGRAM are specified. (It is not written in a DCRAM address.)
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (33th) C0 C1 C2 C3 C4 C5 C6 C7
LSB MSB
: CGROM of a dummy and the character code of CGRAM are specified. (It is not written in a DCRAM address.) : Character code of CGROM and CGRAM is specified. (DCRAM address 00H are rewritten.)
B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (34th) C0 C1 C2 C3 C4 C5 C6 C7
C0 (LSB) to C7 (MSB): Character code of CGROM and CGRAM (8 bits: 256 characters) * : Don't Care [COM positions and set DCRAM addresses]
DCRAM address (HEX) 00 01 02 03 04 05 06 07 08 09 0A 0B COM COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 DCRAM address (HEX) 0C 0D 0E 0F 10 11 12 13 14 15 16 17 COM COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 Dummy is put in to set up a DCRAM address from 00H continuously. DCRAM address (HEX) 18 19 1A 1B 1C 1D 1E 1F COM Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy
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2,A. CGRAM data write (CGRAM writes character pattern data.) CGRAM (Character Generator RAM) has a 4-bit address to store 5x 7 dot matrix character patterns. A character pattern stored in CGRAM can be displayed by specifying the character code (address) by DCROM. The address of CGRAM is assigned to 00H to 0FH. (All the other addresses are the CGROM addresses.) (The CGRAM can store 16 types of character patterns.) [Command format]
0: Select CGRAM_A 1: Select CGRAM_B
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7 1st byte (1st) 0
LSB
0
0
0
0
1
0 0/1 : Selects CGRAM data write mode
MSB
B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (2nd) C0 C5 C10 C15C20 C25 C30
LSB
*
MSB
: Specifies 1st column data (Rewritten into CGRAM address 00H)
B0 B1 B2 B3 B4 B5 B6 B7 3rd byte (3rd) C1 C6 C11 C16C21 C26 C31
LSB
*
MSB
: Specifies 2nd column data (Rewritten into CGRAM address 00H)
B0 B1 B2 B3 B4 B5 B6 B7 4th byte (4th) C2 C7 C12 C17C22 C27 C32
LSB
*
MSB
: Specifies 3rd column data (Rewritten into CGRAM address 00H)
B0 B1 B2 B3 B4 B5 B6 B7 5th byte (5th) C3 C8 C13 C18C23 C28 C33
LSB
*
MSB
: Specifies 4th column data (Rewritten into CGRAM address 00H)
B0 B1 B2 B3 B4 B5 B6 B7 6th byte (6th) C4 C9 C14 C19C24 C29 C34
*
: Specifies 5th column data (Rewritten into CGRAM address 00H)
To specify character pattern data continuously to the next address, specify only character pattern data as follows. The addresses of CGRAM are automatically incremented. Specification of an address is unnecessary. The 2nd to 6th byte (character pattern data) are regarded as one data item, so 200 ns is sufficient for tDOFF time between bytes.
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LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (7th) C0 C5 C10 C15C20 C25 C30
LSB
*
MSB
: Specifies 1st column data (Rewritten into CGRAM address 01H)
B0 B1 B2 B3 B4 B5 B6 B7 6th byte (11th) C4 C9 C14 C19C24 C29 C34
LSB
*
MSB
: Specifies 5th column data (Rewritten into CGRAM address 01H)
B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (12th) C0 C5 C10 C15C20 C25 C30
LSB
*
MSB
: Specifies 1st column data (Rewritten into CGRAM address 02H)
B0 B1 B2 B3 B4 B5 B6 B7 6th byte (16th) C4 C9 C14 C19C24 C29 C34
LSB
*
MSB
: Specifies 5th column data (Rewritten into CGRAM address 02H)
B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (77th) C0 C5 C10C15C20 C25 C30
LSB
*
MSB
: Specifies 1st column data (Rewritten into CGRAM address 0FH)
B0 B1 B2 B3 B4 B5 B6 B7 6th byte (81th) 2nd byte (82th) C4 C9 C14C19C24 C29 C34
LSB
*
MSB
: Specifies 5th column data (Rewritten into CGRAM address 0FH) : Specifies 1st column data (Rewritten into CGRAM address 00H)
B0 B1 B2 B3 B4 B5 B6 B7 C0 C5 C10 C15C20 C25C30
LSB
*
MSB
B0 B1 B2 B3 B4 B5 B6 B7 6th byte (86th) C4 C9 C14 C19C24 C29C34
*
: Specifies 5th column data (Rewritten into CGRAM address 00H)
X0 (LSB) to X3 (MSB) : CGRAM addresses (4 bits: 16 characters) C0 (LSB) to C34 (MSB) : Character pattern data (35 bits: 35 outputs per digit) * : Don't care
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[CGROM addresses and set CGRAM addresses] Refer to ROM code tables.
HEX 00 01 02 03 04 05 06 07 X0 0 1 0 1 0 1 0 1 X1 0 0 1 1 0 0 1 1 X2 0 0 0 0 1 1 1 1 X3 0 0 0 0 0 0 0 0 CGROM address RAM00 (00000000B) RAM01 (00000001B) RAM02 (00000010B) RAM03 (00000011B) RAM04 (00000100B) RAM05 (00000101B) RAM06 (00000110B) RAM07 (00000111B) HEX 08 09 0A 0B 0C 0D 0E 0F X0 0 1 0 1 0 1 0 1 X1 0 0 1 1 0 0 1 1 X2 0 0 0 0 1 1 1 1 X3 1 1 1 1 1 1 1 1 CGROM address RAM08 (00001000B) RAM09 (00001001B) RAM0A (00001010B) RAM0B (00001011B) RAM0C (00001100B) RAM0D (00001101B) RAM0E (00001110B) RAM0F (00001111B)
Positional relationship between the output area of CGRAM
C0
SEGn1
C1
SEGn2
C2
SEGn3
C3
SEGn4
C4
SEGn5
C5
SEGn6
C6
SEGn7
C7
SEGn8
C8
SEGn9
C9
SEGn10
C5
SEGn6
C7
SEGn8
C8
SEGn9
C10
SEGn11
C11
SEGn12
C12
SEGn13
C13
SEGn14
C14
SEGn15
C10
SEGn11
C11
SEGn12
C13
SEGn14
C14
SEGn15
C15
SEGn16
C16
SEGn17
C17
SEGn18
C18
SEGn19
C19
SEGn20
C15
SEGn16
C16
SEGn17
C17
SEGn18
C19
SEGn20
C20
SEGn21
C21
SEGn22
C22
SEGn23
C23
SEGn24
C24
SEGn25
C20
SEGn21
C21
SEGn22
C23
SEGn24
C24
SEGn25
C25
SEGn26
C26
SEGn27
C27
SEGn28
C28
SEGn29
C29
SEGn30
C25
SEGn26
C27
SEGn28
C28
SEGn29
C30
SEGn31
C31
SEGn32
C32
SEGn33
C33
SEGn34
C34
SEGn35
Area that corresponds to 2nd byte (1st column) (Input 1000001*B) Area that corresponds to 3rd byte (2nd column) (Input 1100011*B) Area that corresponds to 4th byte (3rd column) (Input 1010101*B) Area that corresponds to 5th byte (4th column) (Input 1001001*B) Area that corresponds to 6th byte (5th column) (Input 1100011*B)
Note: CGROM_A and CGROM_B (Character Generator ROM A, B) have an 8-bit address to generate 5 x 7 dot matrix character patterns. Each of CGROM_A and CGROM_B can store 240 types of character patterns. The contents of CGROM_A and CGROM_B can be set separately. General-purpose code -01 is available (see ROM code tables) and custom codes are provided on customer's request.
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3,B. ADRAM data write (ADRAM writes symbol data) ADRAM (Additional Data RAM) has a 1-bit address to store symbol data. Symbol data specified by ADRAM is directly output without CGROM and CGRAM. (The ADRAM can store 1 type of symbol patterns for each digit.) The terminal to which the contents of ADRAM are output can be used as a cursor. [Command format]
LSB MSB
B0 B1 B2 B3 B4 B5 B6 B7 1st byte (1st) *
LSB
0: Select ADRAM_A 1: Select ADRAM_B : Selects ADRAM data write mode
*
*
*
1
1
0 0/1
MSB
B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (2nd) C0 * * * * * * * : Sets symbol data (Written into ADRAM address 00H)
To specify symbol data continuously to the next address, specify only character data as follows. The address of ADRAM is automatically incremented. Specification of addresses is unnecessary.
LSB MSB
B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (3rd) 2nd byte (4th) C0
LSB
*
*
*
*
*
*
*
MSB
: Sets symbol data (Written into ADRAM address 01H) : Sets symbol data (Written into ADRAM address 02H)
B0 B1 B2 B3 B4 B5 B6 B7 C0
LSB
*
*
*
*
*
*
*
MSB
B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (25th) C0 * * * * * * * : Sets symbol data (Written into ADRAM address 17H)
A character code setup of 24-Digit is completion in the above work. Furthermore, you have to specify the character codes of a dummy to be ADRAM and 18H-1FH to perform a character code setup from ADRAM address 00H continuously. (In order to carry out the increment of the address of ADRAM automatically and to set a ADRAM address to 00H.)
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LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (26th) C0
LSB
*
*
*
*
*
*
*
MSB
: The sign data of a dummy is specified. (It is not written in an ADRAM address.)
B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (33th) 2nd byte (34th) C0
LSB
*
*
*
*
*
*
*
MSB
: The sign data of a dummy is specified. (It is not written in an ADRAM address.) : The sign data of a dummy is specified. (ADRAM address 00H are rewritten.)
B0 B1 B2 B3 B4 B5 B6 B7 C0 * * * * * * *
C0 : Symbol data (1 bit: 1-symbol data per digit) * : Don't care
[COM positions and ADRAM addresses]
ADRAM address (HEX) 00 01 02 03 04 05 06 07 08 09 0A 0B
COM COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12
ADRAM address (HEX) 0C 0D 0E 0F 10 11 12 13 14 15 16 17
COM COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24
ADRAM address (HEX) 18 19 1A 1B 1C 1D 1E 1F
COM Dammy Dammy Dammy Dammy Dammy Dammy Dammy Dammy
Dummy is put in to set up a ADRAM address from 00H continuously.
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4. GCRAM data write (writes data by the number of COM outputs for digits) GCRAM (Grid Control RAM) has a 5-bit address to control the number of COM outputs for digits. GCRAM outputs specified data directly to COMn, allowing COM outputs to be controlled arbitrarily. It is also possible to supply a large current by connecting a plurality of COMs outside the ML9204. For example, when COM23 and COM24 are connected, the ML9204 has 23 display digits. In this case, the user specifies "23" as the number of display digits. Write grid data at GCRAM addresses 00H and later. Carry out this mode before putting-out-lights mode release. Refer to a "setting operation flow chart" about the details of a setup. Write COM data"0" in the GCRAM address which is not used for incorrect display prevention. [Command format]
LSB MSB
1st byte (1st)
B0 *
LSB
B1 *
B2 *
B3 *
B4 0
B5 0
B6 1
B7 0
MSB
: Selects a GCRAM data write mode.
2nd byte (2nd)
B0 C0
B1 C1
B2 C2
B3 C3
B4 C4
B5 C5
B6 C6
B7 C7
: Specifies COM data. (Written into GCRAM address 00H)
LSB
MSB
3rd byte (3rd)
B0 C8
LSB
B1 B2 B3 B4 B5 B6 B7 C9 C10 C11 C12 C13 C14 C15
MSB
: Specifies COM data. (Written into GCRAM address 00H)
4th byte (4th)
B0 B1 B2 B3 B4 B5 B6 B7 C16 C17 C18 C19 C20 C21 C22 C23
: Specifies COM data. (Written into GCRAM address 00H)
C0 (LSB) to C23 (MSB): Grid control data (24 bits) *: Don't Care Note: To specify additional grid control data, specify the grid control data as shown below. The GCRAM addresses are automatically incremented. The second byte to the fourth byte (for grid data) are treated as a single piece of element and the byte-byte tDOFF can be 200 ns.
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LSB
MSB
2nd byte (5th)
B0 C0
LSB
B1 C1
B2 C2
B3 C3
B4 C4
B5 C5
B6 C6
B7 C7
MSB
: Specifies COM data. (Written into GCRAM address 01H)
B0 B1 B2 B3 B4 B5 B6 B7 4th byte C16 C17 C18 C19 C20 C21 C22 C23 (7th)
LSB MSB
: Specifies COM data. (Written into GCRAM address 01H)
2nd byte (71st)
B0 C0
LSB
B1 C1
B2 C2
B3 C3
B4 C4
B5 C5
B6 C6
B7 C7
MSB
: Specifies COM data. (Written into GCRAM address 17H)
B0 B1 B2 B3 B4 B5 B6 B7 4th byte C16 C17 C18 C19 C20 C21 C22 C23 (73rd)
: Specifies COM data. (Written into GCRAM address 17H)
With the above operations, COM data of up to 24 digits are set. To set other COM data at GCRAM addresses 00H and later, specify dummy symbol data at GCRAM addresses 18H to 1FH (to automatically increment the GCRAM address and set the GCRAM address to 00H).
[GCRAM addresses (digit positions) and COM positions]
GCRAM address (HEX) COM1 COM2 COM3 COM4 COM5
1(00) C0 C0 C0 C0 C0
2(01) C1 C1 C1 C1 C1
3(02) C2 C2 C2 C2 C2 *****
22(15) C21 C21 C21 C21 C21
23(16) C22 C22 C22 C22 C22
24(17) C23 C23 C23 C23 C23
COM20 COM21 COM22 COM23 COM24
C0 C0 C0 C0 C0
C1 C1 C1 C1 C1
C2 C2 C2 C2 C2
C21 C21 C21 C21 C21
C22 C22 C22 C22 C22
C23 C23 C23 C23 C23
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[GCRAM output example] 1. When 4-digit of the 9-digit display requires an output current of 40 mA Number setup of display beams: 9-digit GCRAM setup:4-digit of COM4 and COM5 * Write "0" also in the beam which is not used.
GCRAM address (HEX) COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10
1(00) 2(01) 3(02) 4(03) 5(04) 6(05) 7(08) 8(07) 9(08) 11(09) 11(0A) ...... 23(16) 24(17)
1 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0
0 0 1 0 0 0 0 0 0 0
0 0 0 1 1 0 0 0 0 0
0 0 0 0 0 1 0 0 0 0
0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 0 1 0 0
0 0 0 0 0 0 0 0 1 0
0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 ......
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0
1 Cycle
COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10
COM1 COM2 Strap COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 GRID1 GRID2 GRID3 GRID4 GRID5 GRID6 GRID7 GRID8 GRID9
* Strapping COM4 and COM5 brings display digits to 9 digits, and a current of 50 mA can be supplied.
Dsiplay tube
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2. When only one digit of the 22-digit display requires an output current of 60 mA Number setup of display beams:22-digit GCRAM setup:1-digit of COM1 and COM23 and COM24 * Write "0" also in the beam which is not used.
GCRAM address (HEX) COM1 COM2 COM3 1(00) 1 0 0 2(01) 0 1 0 3(02) 0 0 1 4(03) 0 0 0 5(04) 0 0 0 6(05) 0 0 0 7(08) 0 0 0 8(07) 0 0 0 9(08) 0 0 0 11(09) 0 0 0 ...... ...... 22(15) 0 0 0 23(16) 0 0 0 24(17) 0 0 0
COM22 COM23 COM24
0 1 1
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
1 0 0
0 0 0
0 0 0
1 Cycle Display tube
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COM1 COM2 COM3 Strap COM1 COM2 COM3 GRID1 GRID2 GRID3
COM22 COM23 COM24
COM22 COM23 COM24
GRID22
* Strapping COM1, COM23 and COM24 brings display digits to 22 digits, and a current of 75 mA can be supplied.
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5. Display duty set (writes display duty value to duty cycle register) Display duty adjusts brightness in 1024 stages using 10-bit data. When power is turned on or when the RESET signal is input, the duty cycle register value is "0". Always execute this instruction before turning the display on, then set a desired duty value. [Command format]
LSB MSB
B0 B1 B2 B3 B4 B5 B6 B7 1st byte (1st) 2nd byte (2nd) D0 D1
LSB
*
*
1
0
1
0
MSB
: Selects display duty set mode and sets duty value (lower 2 bits)
B0 B1 B2 B3 B4 B5 B6 B7 D2 D3 D4 D5 D6 D7 D8 D9 : sets duty value (upper 8 bits)
D0 (LSB) to D9 (MSB) : Display duty data (10 bits: 1024 stages) * : Don't care [Relation between setup data and controlled COM duty]
HEX 000 001 002 D0 0 1 0 D1 0 0 1 D2 0 0 0 D3 0 0 0 D4 0 0 0 D5 0 0 0 D6 0 0 0 D7 0 0 0 D8 0 0 0 D9 0 0 0 COM duty 0/1024 1/1024 2/1024
3BE 3BF 3C0 3C1
0 1 0 1
1 1 0 0
1 1 0 0
1 1 0 0
1 1 0 0
1 1 0 0
0 0 1 1
1 1 1 1
1 1 1 1
1 1 1 1
958/1024 959/1024 960/1024 960/1024
3FF
1
1
1
1
1
1
1
1
1
1
960/1024
The state when power is turned on or when RESET signal is input.
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6. Number of digits set (writes the number of display digits to the display digit register) The number of digits set can display 9 to 24 digits using 4-bit data. When power is turned on or when a RESET signal is input, the number of digit register value is "0". Always execute this instruction to change the number of digits before turning the display on. [Command format]
LSB MSB
B0 B1 B2 B3 B4 B5 B6 B7 1st byte K0 K1 K2 K3 0 1 1 0 : selects the number of digit set mode and specifies the number of digit value
K0 (LSB) to K3 (MSB) : Number of digit data (4 bits: 24 digits) * : Don't care [Relation between setup data and controlled COM]
* When the number of COM is one at 1 digit
HEX 0 1 2 3 4 5 6 7 K0 0 1 0 1 0 1 0 1 K1 0 0 1 1 0 0 1 1 K2 0 0 0 0 1 1 1 1 K3 0 0 0 0 0 0 0 0 Number of digits of COM 1-24(COM1 to 24) 1-9(COM1 to 9) 1-10(COM1 to 10) 1-11(COM1 to 11) 1-12(COM1 to 12) 1-13(COM1 to 13) 1-14(COM1 to 14) 1-15(COM1 to 15) HEX 0 1 2 3 4 5 6 7 K0 0 1 0 1 0 1 0 1 K1 0 0 1 1 0 0 1 1 K2 0 0 0 0 1 1 1 1 K3 1 1 1 1 1 1 1 1 Number of digits of COM 1-16(COM1 to 16) 1-17(COM1 to 17) 1-18(COM1 to 18) 1-19(COM1 to 19) 1-20(COM1 to 20) 1-21(COM1 to 21) 1-22(COM1 to 22) 1-23(COM1 to 23)
The state when power is turned on or when RESET signal is input.
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7. All display lights ON/OFF set (turns all display lights ON or OFF) All display lights ON is used primarily for display testing. All display lights OFF is primarily used for display blink and to prevent malfunction when power is turned on. [Command format]
LSB MSB
B0 B1 B2 B3 B4 B5 B6 B7 1st byte L H * * 1 1 1 0 : Selects all display lights ON or OFF mode
L, H : Display operation data * : Don't care [Set data and display state of SEG and AD]
L 0 1 0 1 H 0 0 1 1 Display state of SEG and AD Normal display Sets all outputs to Low Sets all outputs to High Sets all outputs to High * Priority is given to an all-points light command.
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C. Key scan stop This command stops key scanning and makes ROW1 to ROW5 outputs "Low" and the INT output "Low".
[Command format]
LSB MSB
1st byte
B0 *
B1 *
B2 *
B3 *
B4 0
B5 0
B6 1
B7 1
: stops key scanning.
*: Don't Care
D. Key data output This command puts the pin in the output mode and causes the pin to output the scanned switch data. The DI/O pin outputs 42-bit switch data at the rise of a clock. When the CS pin goes high, the DI/O pin enters the output mode. "R1, R2, R3 = 0" means turning a control knob clockwise. "R1, R2, R3 = 1" means turning a control knob counterclockwise. Contact count bits are Q11(LSB) to Q13(MSB), Q21(LSB) to Q23(MSB), and Q31(LSB) to Q33(MSB). [Command format]
LSB MSB
1st byte *:
B0 *
B1 *
B2 *
B3 *
B4 1
B5 0
B6 1
B7 1
: outputs key data.
Don't Care
[COL input and ROW output key-switch matrix]
ROW1 COL1 COL2
S12 S22 S32 S42 S52
ROW2
ROW3
ROW4
ROW5
S11
S21
S31
S41
S51
COL3
S13 S23 S33 S43 S53
COL4
S14 S24 S34 S44 S54
COL5
S15 S25 S35 S45 S55
COL6
S16 S26 S36 S46 S56
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[Output Data Format] Output data: 42 bits 5 x 6 push switch data: 30 bits Encoder switch data: 12 bits
Bit Output Data Bit Output Data Bit Output Data Bit Output Data 1 S11 13 S31 25 S51 37 Q22 2 S12 14 S32 26 S52 38 Q23 3 S13 15 S33 27 S53 39 R3 4 S14 16 S34 28 S54 40 Q31 5 S15 17 S35 29 S55 41 Q32 6 S16 18 S36 30 S56 42 Q33 7 S21 19 S41 31 R1 8 S22 20 S42 32 Q11 9 S23 21 S43 33 Q12 10 S24 22 S44 34 Q13 11 S25 23 S45 35 R2 12 S26 24 S46 36 Q21
Sij: i = ROW1 to 5; j = COL1 to 6 Sij = 1: switch ON Sij = 0: switch OFF
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Keyscan Keyscanning is started only when depression or release of any key is detected in order to minimize noise caused by scanning signal. Then, keyscanning is continued until the keyscan stop mode is sent from a microcomputer. The INT pin goes to the high level at the completion of 1-cycle scanning after the keyscan start, so the (high level) signal sent from the INT pin can be used as an interrupt signal. [Keyscan Timing and Cycles]
ROW1
ROW2
ROW3
ROW4
ROW5 1 keyscan cycle INT
Depress/Release
keyscan stop
Keyscanning cannot be stopped by selecting the keyscan stop mode only once if: - keyscanning is started after depression or release of any key is detected, and then - a key is depressed or released again before the keyscan stop mode is selected. To stop keyscanning, it is required to select the keyscan stop mode once again.
Depress
Depress
Release
INT CS
Keyscan
Keyscan
KS KS: Keyscan stop mode
KS
KS
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The rotary encoder switch function As Figure 1 shows, the rotary encoder switch circuit is consisted of Phase detection, Interrupt generation, Up/down counter, Direction latch and Parallel-in serial-out shift register.
A B
Phase Detection
UP DOWN
Interrupt Generation
for INT
UP/DOWN Counter
Q3 Q2 Q1
Direction Latch
R1
P-in/S-out Shift Register
Output data
The Rotary Encoder Switch Circuit
1. Phase detection 1-1. Clockwise rotation The input A and B have a chattering absorption circuit of 256 s period. When signal A and B input as shown below, the phase detection circuit outputs UP signal after the chattering absorption period. At this time, the output INT also goes to high level, so this signal can be used as an interrupt. The INT stays High level until the keyscan stop mode is selected.
A
B
chattering absorption time
UP (internal)
INT
The Input and Output Timing in the Case of Clockwise Rotation
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1-2. Counterclockwise rotation When signal A and B input as shown below, the phase detection circuit outputs Down signal after the chattering absorption period. At this time, the output INT also goes to High level. The INT stays High level until the keyscan stop mode is selected.
A
chattering absorption time
B
DOWN (internal)
INT
The Input and Output Timing in the Case of Counterclockwise Rotation
2. UP/DOWN COUNTER When the UP/DOWN COUNTER is input UP, it counts up and when it is input DOWN, it counts down. But if the UP/DOWN COUNTER is incremented beyond "111", it stays "111".
A
B Q1, Q2, Q3 100 010 110 001 101 011 111 111
Counter Overflow
3. Direction latch When the Direction latch is input DOWN the output R1 goes "1". But if the UP pulse is input and the count value changes to a positive value, the output R1 goes to "0".
A
B
R1 Q1, Q2, Q3 100 010 100 000 100 010
Direction Latch
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F. Standby mode set (Display all switched off and an oscillation stopped) Standby mode realizes low power consumption of VDD, VSEG, and VCOM by all switching off a display, stopping an oscillation of an external (COM is fixed to Low) oscillation child, and stopping internal operation completely. All display lights OFF is primarily used for display blink and to prevent malfunction when power is turned on. * If a RESET signal is inputted during standby mode execution, standby mode is canceled, and keep in mind it that all states will be initialized. [Command format]
LSB MSB
B0 B1 B2 B3 B4 B5 B6 B7 1st byte * * * * 1 1 1 1 1 : Standby mode is specified.
* : Don't care [Release standby mode] Release in standby mode is performed in falling of CS. (An oscillation child's oscillation is started) Data input will become possible if an oscillation is stabilized. (Please return brought-down CS high-level before data input) When you display after standby mode release since it is all putting out lights although the setting state is held, please cancel all putting-out-lights modes (in usual mode). * Please do not input a shift clock into CP until an oscillation is stabilized. (Data will be given) tRSON (oscillation standup time) changes with oscillation children who use it. Please make reference an oscillation child's data to be used.
CS
Set it as 200nsec. tRSON
* May not place the section.
Data input
CP
DA
B0 B1B2 B3 B4 B5 B6 B7
Standby release, Standby section Usually, a state of operation (all putting-out-lights states)
LSB
1st byte
MSB
Standby state
OSC0
0.9Vp-p
Vp-p
Oscillation stop state
Oscillation unstable state (oscillation standup time)
Oscillation stable state
Oscillation start
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SETTING FLOWCHART
(Power applying included)
Apply VDD
RESET execution
Apply VSEG/VCOM
All display lights OFF
Status of all outputs by RESET
Number of digits setting
Display duty setting Select a RAM to be used
DCRAM_A or B Data write mode
Address is automatically incremented
CGRAM_A or B Data write mode (with address setting)
Address is automatically incremented
ADRAM_A or B Data write mode
Address is automatically incremented
GCRAM Data write mode
Address is automatically incremented
DCRAM_A or B Character code
CGRAM_A or B Character code
ADRAM_A or B Character code
GCRAM code
NO
DCRAM Is character code write ended?
YES
NO
CGRAM Is character code write ended?
YES
NO
ADRAM Is character code write ended?
YES
NO
GCRAM write ended?
YES
YES
Another RAM to be set?
NO
Releases all display lights OFF mode
End of setting
Display operation mode
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ML9204-xx
POWER-OFF FLOWCHART
Display operation mode
Turn off VSEG/VCOM
Turn off VDD
APPLICATION CIRCUIT
5 x 7 dot matrix fluorescent display
ANODE ANODE ANODE GRID (SEGMENT) (SEGMENT) (SEGMENT) (DIGIT)
VDD Output port VDD
2
VDD
CS CP DI/O
35
35
24
COM1-24
*1
VSEG
ADA,ADB SEGB1-B35 SEGA1-A35
R VSEG / VCOM
MCU
GND *2
INT
RESET
ML9204-xx
VCOM
OSC0 OSC1 L-GND D-GND A1-3 B1-3 ROW1-5 COL1-6
ZD
*3 Crystal oscillation or Ceramic oscillation
5x6Key matrix and rotary switch
*1 The VSEG and VCOM voltages depend on the fluorescent display tube used. Adjust the value of the constants R and ZD to the VSEG and VCOM voltages used. *2 The wiring trace between the OSC0 pin and the resonator should be kept as short as possible, and the GND traces should be provided along both sides of the wiring trace. *3 Adjust the capacitance of the capacitor depending on the type of the oscillator used. (Refer to the data of oscillator used.)
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PACKAGE DIMENSIONS
(Unit: mm)
QFP128-P-1420-0.50-K
Mirror finish
5
Notes for Mounting the Surface Mount Type Package
Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised
Epoxy resin 42 alloy Solder plating (5m) 1.19 TYP. 4/Nov. 28, 1996
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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REVISION HISTORY
Document No.
PEDL9204-01 PEDL9204-02
Date
Jan. 8, 2003 Oct. 12, 2004
Page Previous Current Edition Edition
- 4 - 4
Description
Preliminary edition 1 Pin description added
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NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not, unless specifically authorized by Oki, authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2004 Oki Electric Industry Co., Ltd.
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